1. Field of the Invention
The present invention relates generally to integrated circuit device assembly and, more particularly, to testing an integrated circuit device for open circuits and short circuits in the power and ground pins.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits are generally mass produced by fabricating thousands of identical circuit patterns on a single semiconductor wafer and subsequently dividing them into identical die or chips. To produce the integrated circuit, many commonly known processes are used to modify, remove, and deposit material onto the semiconductor wafer, which is generally made of silicon. Processes such as ion implantation, sputtering, etching, chemical vapor deposition, and variations thereof are among the processes commonly used. These processes are often selectively applied to an integrated circuit through the use of a masking process. In the masking process, a photomask containing patterned structures to be fabricated is created, and the wafers are coated with a photo-lithographic material, such as a photoresist. The resist-coated wafer is exposed to ultraviolet light through a photomask to soften or harden parts of the photoresist depending on the type of photoresist used. Once the softened parts of the photoresist are removed, the wafers are treated by one of the processes discussed above to modify, remove, or replace the part unprotected by the photoresist, and then the remaining photoresist is stripped from the semiconductor wafer. The masking process permits specific areas of the integrated circuit to be modified, removed, or replaced.
Once the active and passive parts are fabricated in and on the wafer surface, one or more layers of conductive material, such as metal, for electrically connecting circuit components is added, and a protective layer is deposited over the silicon wafer. The wafer is visually evaluated and electrically tested to determine which integrated circuit die are good so that they may be packaged for use. After the semiconductor devices are tested in wafer form, they may be separated through a sawing process. The electrically good die are generally packaged in a protective coating. The packaged device may again be tested using various testing systems.
Electrical tests may be performed numerous times during and after wafer fabrication. The integrated circuits are generally tested while the integrated circuits are still in wafer form, after the integrated circuits have been excised into single die, and once the integrated circuit has been packaged for use in a system. Various pieces of electrical test equipment are used to check for open circuits and short circuits in the power, ground, and signal paths of each integrated circuit. Parametric tests, functional tests, and continuity tests, among others, may be performed. Often, the test equipment used to test the integrated circuits electrically vary from test to test, often requiring manual movement of the parts from one piece of test equipment to another. Each act of human intervention and each act of inserting and removing a wafer, integrated circuit die, or packaged integrated circuit from a piece of test equipment adds an additional risk for injecting failures into the integrated circuit device. Most of the wafer fabrication process is an automated process which minimizes human contact with the integrated circuits. Not only does this increase volume production, but it minimizes contamination and breakage due to human intervention.
Packaged integrated circuits include an additional component which may be susceptible to failure. Packaged integrated circuits may include conductive pins or balls, for example, which may be used to carry signals to and from active circuits on the device. Continuity from the device to the pins or balls is important to the incorporation of the packaged device into a system. Thus, various tests may be performed on various pieces of test equipment to insure full functionality and continuity of the packaged integrated circuit. However, the insertion and re-insertion of devices into various test sockets increases the likelihood of pin/ball breakage. It would be advantageous to minimize the movement of integrated circuit devices between pieces of test equipment, thereby reducing any additional human intervention while still insuring that all necessary electrical tests are conducted.
The present invention may be directed to addressing one or more of the problems set forth above.